The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, field effect transistors (FETs) typically include active regions and gate structures over the active regions. Conductive features, such as contacts and vias, are formed on the FETs for providing electrical connection from a terminal (e.g., source/drain/gate) of an FET to terminal(s) of another FET. Traditionally, vias on gate (or gate vias) are restricted to landing areas away from the active regions of the FETs. This is to prevent the gate vias from being accidentally connected to the sources or drains located in the active regions due to process variation. This creates issues, especially for FETs having many gate vias, because there may not be enough landing areas outside the active regions on a semiconductor device.